1. Field of the Invention
The present invention relates to a semiconductor substrate and a method of manufacturing the same and, more particularly, to the structure of a MOS transistor using buried element isolation and a method of manufacturing the MOS transistor.
2. Description of the Related Art
In an integrated circuit using buried element isolation region, impurity ion concentrations in a channel region and a layer therebelow for determining the characteristics of a MOS transistor are controlled as follows. That is, before a gate electrode wiring layer is formed, the impurity ions are directly implanted in a semiconductor substrate from the upper direction. On the other hand, after a gate electrode wiring layer is formed, the impurity ions are implanted through the gate electrode wiring layer. In this case, "ion implantation for controlling impurity concentrations" means both shallow channel ion implantation for controlling a threshold value of the channel region, in which impurity ions are implanted in a shallow surface of the semiconductor substrate, and deep channel ion implantation for preventing a punchthrough phenomenon, in which impurity ions are implanted in a deep portion separated from the surface of the semiconductor substrate. As shown in FIG. 1, for example, an inversion preventing impurity diffusion region 21 in a buried element isolation region 3 for isolating an element #1 from an element #2 is formed as follows. That is, immediately after a groove 2 is formed in a semiconductor substrate 1, impurity ions are implanted in the semiconductor substrate 1 of the bottom portion of the groove 2 by means of normal ion implantation having an ion implantation angle of 7.degree. or less using a mask material for forming the groove 2 as a mask, or impurity ions are uniformly implanted in the bottom and side walls of the groove 2 by means of oblique rotation ion implantation, or impurity ions having different concentrations are implanted in the bottom portion of the groove 2 and the side walls of the groove 2, respectively, by means of the normal ion implantation and the oblique rotation ion implantation. In FIG. 1, reference numerals 20, 7, and 8 denote a channel region, a gate electrode wiring layer, and a gate oxide film, respectively. With above element isolation techniques, both the element isolation characteristic of the buried element isolation region 3 and the various characteristics of a MOS transistor surrounded by the buried element isolation region 3 have been conventionally controlled.
According to the above conventional method of manufacturing a semiconductor device, since the characteristics of the MOS transistor depend on the structure of the buried element isolation regions which are in contact with each other, the element isolation characteristic and the characteristics of the MOS transistor cannot be independently determined. For this reason, required element characteristics cannot be easily obtained. In particular, as shown in FIG. 1, in a buried element isolation structure, concentration of the electric field caused by the gate electrode wiring layer 7 occurs near an element region 20a at a corner of the substrate 1 of an upper end of the groove 2. For this reason, a threshold value Vth of the channel region 20 is decreased, or the threshold value Vth is conspicuously varied due to an increase in electron trap in the gate oxide film 8 over time. Thus the reliability of the element may be degraded.
In a micropatterned MOS transistor, however, when impurity ions are locally implanted from the upper direction by means of shallow channel ion implantation, impurity ions having concentration different from that of the substrate surface at the central portion of the channel region 20 cannot be implanted near the element region 20a at the corner of the substrate of the upper end of the groove 2 by currently available photolithography due to limitations of processing dimensions and adjustment precision. In a region 1a below the channel region 20, as shown in FIG. 2, deep channel ion implantation having an impurity concentration different from that near the substrate surface of the channel region 20 is required to prevent a punchthrough phenomenon caused by connecting a depletion layer 22 to a depletion layer 23 between the source and the drain regions. However, when the deep channel ion implantation is performed at an excessively high concentration, a back gate effect is degraded. For this reason, the deep channel ion implantation has an optimal impurity concentration. This optimal value does not coincide with each of the concentrations of the inversion preventing impurity diffusion region 21, the portion near the element region 20a at the substrate corner of the upper end of the groove 2, and the substrate surface at the central portion of the channel region 20. In the buried element isolation structure having the inversion preventing impurity diffusion region 21 obtained by uniformly implanting an impurity in the side walls of the groove 2, when the impurity concentration is too high, the back gate effect is degraded. When the impurity concentration is too low, the threshold value of a portion near the element region 20a at the substrate corner of the upper end of the groove 2 may not be controlled.